Superscalar instruction issue

A superscalar processor contains multiple copies of the datapath hardware to execute multiple instructions simultaneously. Figure 7.67 shows a block diagram of a two-way superscalar processor that fetches and executes two instructions per cycle. The datapath fetches two instructions at a time from the instruction memory. It has a six-ported register file to read four source operands and write Multiple Instruction Issue. Multiple Instruction Issue. Multiple instructions issued each cycle better performance increase instruction throughput decrease in CPI (below 1) greater hardware complexity, potentially longer wire lengths harder code scheduling job for the compiler Superscalar processors Superscalar Issues to be considered Parallel decoding - more complex task than in scalar processors. -High issue rate can lengthen the decoding cycle therefore use predecoding. -partial decoding performed while instructions are loaded into the instruction cache Superscalar instruction issue - A higher issue rate gives rise to higher Multiple Issue (Superscalar) • basic pipeline: single, in-order issue • first extension: multiple issue (superscalar) • still in-order • future topics • what if older instruction in issue "pair" (inst0) stalls? • younger instruction (inst1) stalls too, cannot pass it A superscalar processor uses dynamic scheduling, e.g. the hardware controls the issue of instruction dynamically. For static scheduling the LIW architecture (long instruction word) (now VLIW very long..) depends on a compiler to schedule concurrent instructions and rearranging them into a long instruction word, typically 120-200 bits. A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution CS232 12. Superscalar Fall 2021 Superscalar (III) Instruction Issue Policy (cont.)-Example:• Assume a superscalar pipeline is capable of fetching and decoding 2 instructions at a time-Instructions are fetched and decoded in pair.The next two instructions must wait to be decoded until the pair of decode pipeline stages has cleared. The issue rate defines the maximum number of instructions a superscalar processor can issue in each cycle. The design space of issue policy is complex. As shown in the figure, it consists of four major aspects. The first two define how false data and unresolved control dependencies are coped with during instruction issues. Superscalar architectures enable multiple operations to be launched by a single instruction issue. This is achieved through the incorporation of multiple arithmetic logic units (ALUs), including both floating-point and integer/logical functional units, among others. tion and instruction issue. This paper addresses these and. related issues by proposing (i) partitioning of the instruction. window into multiple blocks, each holding a dynamic code. sequence; (ii